Multiplex addressing using auxiliary pulses

ABSTRACT

PCT No. PCT/GB94/01503 Sec. 371 Date Mar. 14, 1996 Sec. 102(e) Date Mar. 14, 1996 PCT Filed Jul. 11, 1994 PCT Pub. No. WO95/02235 PCT Pub. Date Jan. 19, 1995In a three-slot addressing scheme for a liquid crystal optical modulator, where the data waveforms comprise a data section, a charge-balancing section and a further section, the form of the further section depends upon the sequence of data waveforms. The further section or pair of adjacent further sections comprises a pair of pulses of opposite polarities which charge-balance each other. The order in which these pulses occur in the pair enhances the effect of the adjacent data section to aid or inhibit switching as appropriate. This facilitates a shorter line address time.

BACKGROUND OF THE INVENTION

This invention relates to a method of addressing a matrix of bistablepixels which are defined by areas of overlap between members of a firstset of electrodes on one side of a layer of ferroelectric material andmembers of a second set of electrodes, which cross the members of thefirst set, on the other side of the material, in which method blankingsignals are applied to the members of the first set of electrodes toeffect blanking before unipolar select signals are applied thereto oneby one to effect writing to the corresponding pixels by simultaneouslyapplying a chosen data waveform to each member of the second set ofelectrodes, the data waveforms each including a data section coincidingwith a select signal, in between a charge-balancing section whichcharge-balances the data section and a further section.

A known drive scheme for multiplex addressing FLCDs, known as lineblanking, is described in GB 2173336, and shown diagrammatically inFIG. 1. The row electrodes of the device are scanned with a "blank"waveform 6 of amplitude Vb, followed by a `select` waveform 3 ofamplitude Vs. One of two data waveforms "unchanged" 8 or "on" 10, eachof amplitude Vd, is applied to each column electrode simultaneously withthe occurrence of each select waveform, and is chosen in accordance withthe required state of the pixel in the column which is also in the rowhaving the `select` waveform applied to it. The resultant writingwaveforms appearing across the pixel are shown at 12 and 14. The `blank`waveform 6 sets the pixels of the row to a dark state regardless ofwhich data signal it combines with, i.e. whether resultant waveforms 10or 12 appear across the pixels. When a row is neither being selected norblanked, i.e. the non-select signal 4 is applied to the row, theresultant waveforms 16 or 18 appear corresponding to the data signals 8,10 neither of which change the state of the pixels.

This drive scheme is suitable for use in the so called `inverse` mode ofoperation of the ferroelectric material where the voltage which switchesthe pixel given a certain pulsewidth is lower than that which leaves itunchanged. However, it is unsuitable for use in the normal mode, wherethe opposite is true, although operation in this mode is desirable dueto the lower drive voltages required.

FIG. 2 shows the switching characteristic, pulsewidth W versus voltageV, of a typical ferroelectric material such as liquid crystal. The partof the characteristic within which switching occurs is denoted as 100and the part within which switching does not occur is denoted as 101. Itcan be seen that the curve is much less steep in the normal mode part102 than in the inverse mode part 103, so that the data voltages Vd mustbe much larger in order to ensure that the applied pulses fall withinthe correct part of the switching characteristic even when outsidefactors such as temperature change cause it to vary. This leads to theproblem that the data voltages alone (i.e. combined with a non-selectpulse) may be sufficient to cause unwanted switching where datawaveforms of opposite senses follow each other and effectively extendthe widths of the pulses.

The scheme shown in FIG. 3 has been proposed by T. Numao and M. Koden ina paper "Driving waveforms of partial writing scheme for FLCD" in"Displays" vol. 14 no. 3 at pages 139-143 (July 1993) to alleviate thisproblem. In this scheme, known as a `three-slot` scheme, the datawaveforms "unchanged" 24 and "on" 26 each have three sections. Themiddle sections, which coincide with the select pulse 28, are ofopposite polarities, and the positive and negative parts of eachwaveform are in the same order so that a pulse of a particular polarityis never followed immediately by another of the same polarity. Althoughthis scheme reduces the risk of unwanted switching, it also slows downthe addressing of the matrix since another time period is added to eachwaveform. The non-select and blank waveforms are denoted by 104 and 105respectively in FIG. 3.

SUMMARY OF THE INVENTION

The present invention seeks to alleviate the problems of the known priorart.

According to one aspect of the present invention, a method as defined inthe first paragraph is characterised in that each single further sectionor pair of further sections occurring between successive data sectionsapplied to any electrode of the second set is itself charge-balanced andcomprises at least two non-zero portions.

With this method it is possible to increase the addressing speed of thethree-slot scheme by arranging for the polarities of the furthersections to reinforce the effect of the adjacent data sections whenselected. Thus the pulsewidth of the data section and hence also theselect signal may be reduced, decreasing the line address time.

Preferably the further section or pair of adjacent further sections hasno zero portion, so that the method can be implemented with a two-statedata driver, providing an advantage over the prior art three-slotscheme.

In an embodiment wherein switching is effected by a data section havingthe opposite polarity to the select signal (i.e. the `normal` mode), atleast the portion of the further section which portion is adjacent thedata section which affects switching has the same polarity as the datasection.

In an embodiment wherein switching is effected by a data section havingthe same polarity as the select signal (i.e. the `inverse` mode), atleast the portion of the further section which portion is adjacent thedata section has a polarity which is opposite to the polarity of thedata section.

According to another aspect the invention provides an optical modulatorapparatus comprising an optical modulator having a matrix of bistablepixels defined by areas of overlap between members of a first set ofelectrodes on one side of a layer of ferroelectric material, and membersof a second set of electrodes, which cross the members of the first set,on the other side of the layer, and an addressing waveform generatorhaving a first set of outputs connected to respective members of thefirst set of electrodes, and a second set of outputs connected torespective members of the second set of electrodes, the generator beingarranged to generate blanking signals followed by select signals at eachoutput of the first set and, simultaneously with each select signal, achosen data waveform at each output of the second set, the datawaveforms each including a data section coinciding with a select signal,in between a charge-balancing section, which charge-balances the datasection, and a further section, characterised in that the generator isarranged to generate the data waveforms in such manner that each singlefurther section, or pair of further sections occurring betweensuccessive data sections at each output of the second set is itselfcharge balanced and comprises at least two non-zero portions.

BRIEF DESCRIPTION OF THE DRAWINGS

In order that the invention may be more readily understood, referencewill now be made to the accompanying diagrammatic drawings, in which:

FIG. 1 shows waveforms used in a known addressing scheme;

FIG. 2 is a diagram of a typical switching characteristic for a bistableferroelectric material;

FIG. 3 shows waveforms used in another known addressing scheme;

FIG. 4a shows various combinations of data waveforms according to oneembodiment of the present invention;

FIG. 4b shows the corresponding resultant waveforms across a selectedpixel, for the normal mode of operation;

FIGS. 5a and 5b show waveforms corresponding to the waveforms of FIG. 4aand 4b for the inverse mode of operation;

FIG. 6 shows a pixel matrix and an address waveform generator therefor;

FIG. 7 is a block diagram of a possible construction for part of thewaveform generator of FIG. 6; and

FIG. 8 shows a possible form of a logic circuit included in theconstruction of FIG. 7.

DETAILED DESCRIPTION OF THE INVENTION

Referring to FIGS. 4a and 5a, the eight possible different successionsof three data waveforms are shown.

In FIG. 4a, `1` indicates a waveform which when combined with a negative`select` signal (eg 28 in FIG. 3) effects switching of the pixel, and`2` indicates a waveform which leaves the state of the pixel unchanged.In FIG. 5a, the opposite is the case; that is, `1` is a non-switchingwaveform and `2` is a switching waveform.

FIGS. 4b and 5b show the corresponding resultant waveforms across apixel in the selected row; that is the pixel which is defined by thearea of overlap between the member of the second set of electrodes towhich the data in FIGS. 4a and 5a is being applied, and the member ofthe first set of electrodes to which the select signal is being appliedsimultaneously with the middle data waveform. In the drawings, the datasections of each waveform, and the resultant in the case of the middledata waveform are shaded for clarity, the further sections of the datawaveforms are shown in broken lines and the charge-balancing sectionsare shown in continuous lines, also for clarity. The data,charge-balancing and further sections of each data waveform are each oflength T.

It will be understood that in FIG. 4, the upper four cases showswitching of the selected pixel, and the lower four cases shownon-switching, whilst the reverse is true for FIG. 5b.

It can be seen from the drawings that each data waveform comprises adata section which in this example is a uni-polar pulse 34, acharge-balancing section 36, which is a unipolar pulse of the oppositepolarity, and a further section 38. For a `1` waveform, thecharge-balancing section 36 is followed by the data section 34, which isfollowed by the further section 38. For a `2` waveform, the positions ofthe charge-balancing and further sections are reversed.

The form which the further section of each waveform takes depends uponthe adjacent waveform. Where a further section 38 occurs between a datasection 34 and a charge-balancing section 36, it takes the form of apair of pulses of opposite polarities which charge-balance each other,ie. have equal areas. This is the case when a waveform having a datasection of one polarity is followed by a waveform having a data sectionof the same polarity (i.e. 1,1 or 2,2). When a pair of further sections38 occur successively, the pair takes the form of a single pair ofpulses of opposite polarities which charge-balance each other. This isthe case when a `1` waveform is followed by a `2` waveform.

For operation in the normal mode shown in FIGS. 4a and b, the portion ofeach such pair of pulses which is adjacent a data section of a switchingwaveform `1` has the same polarity as the data section (i.e. the upperfour cases). This aids switching by ensuring that a pulse of the samepolarity closely follows the `select`/switch pulses 33 in the resultantwaveform, and allows the pulsewidths to be reduced when compared withknown three-slot schemes, where a switching pulse is surrounded bypulses having negative or zero voltage levels.

The pulse pairs of the further sections also inhibit switching where thedata section of an `unchanged` data waveform `2` combines with theselect signal (i.e. the lower four cases). In these cases, the pulsepairs ensure that there is a pulse of the opposite polarity immediatelyor closely preceding the `select`/`unchanged` pulse 35 of the resultantwaveforms. It will be appreciated that the further section 38 occurringbetween the data sections of two `unchanged` waveforms 2 can have thepolarity of each portion reversed.

Referring now to FIGS. 5a and b, for operation in the inverse mode, theportion of the pulse pair which is adjacent the data section of therespective data waveform has the opposite polarity to that of the datasection. Referring to the upper four cases, this ensures that an`unchanged`/`select` pulse 37 in the resultant waveform is immediatelyfollowed by a pulse having the opposite polarity, thus inhibitingswitching. Similarly the switching/select pulse 39 in the resultantwaveform is immediately preceded by a pulse of the same polarity, aidingswitching.

In FIG. 6 a matrix-type liquid crystal cell 41 comprises in known mannera pair of transparent plates which are superimposed one upon the otherwith a small spacing therebetween which contains ferroelectric liquidcrystal material. The cell comprises a matrix of picture elements(pixels) which are defined by areas 42 of overlap between members of afirst set of parallel transparent electrodes 44 provided on the innersurface of one plate, i.e. on one side of the liquid crystal material,and members of a second set of parallel transparent electrodes 43provided on the inner surface of the other plate, i.e. on the other sideof the liquid crystal material. The electrodes 43 and 44 are orientedsubstantially orthogonal to each other and each corresponds to arespective line of pixels. (With the orientation shown each electrode 43of the second set corresponds to a respective column of pixels and eachelectrode 44 of the first set corresponds to a respective row).

The cell 41 is addressed by means of an addressing waveform generator 45via a first set of conductors 47 which are connected to respectivemembers of the first set of electrodes 44 and a second set of conductors46 which are connected to respective members of the second set ofelectrodes 43. For each pixel the resulting electric field appliedthereacross determines the alignment of the liquid crystal molecules andhence the optical state of that pixel.

FIG. 7 is a block diagram of a possible construction for part of thewaveform generator 45 of FIG. 6, more particularly that part whichgenerates the data waveforms of FIG. 4a or FIG. 5a for application tothe n conductors 46 of FIG. 6.

The part of the waveform generator 45 shown in FIG. 7 comprises a clockpulse generator 50, a data store 51 provided with a row addressgenerator 52 and an n-position column address generator 53, a logiccircuit 54, a six-position cycling slot counter 55, a decoder 56, firstand second shift registers 57 and 65 respectively, a multiple latch 58,column conductor drivers 59, and frequency divider-by-ns 60 and 66. Theclock pulse generator 50 controls the store 51, the column addressgenerator 53, and the registers 65 and 57 directly, and the latch 58 andcounter 55 via the dividers 60 and 66 respectively. The parallel outputof the counter 55 controls the logic circuit 54 directly, and the rowaddress generator 52 via the decoder 56. The decoder 56 is constructedto generate an output, and thereby increment the row address generator52, each time the contents of the counter 55 change from three to four(slot four to slot five). An input 61 of the circuit 54 receives datafrom the data store 51, and an input 62 thereof receives data from theserial output 63 of the further store or second register 65. A firstoutput 67 of the circuit 54 feeds the serial input 64 of the firstregister 57, and a second output 68 of the circuit 54 feeds the serialinput 69 of the second register 65. The parallel output of the firstregister 57 feeds the column drivers 59 via the latch 58.

The output frequency of the clock pulse generator 50 is such that 6 nclock pulses occur during each of the complete data waveforms (datasection plus charge-balance section plus further section) shown in FIGS.4a or 5a i.e. 2 n clock pulses during each section. The data store 51stores the pixel data required for the display device 41 of FIG. 6 inthe same format, i.e. in rows and columns. Each row of data is read outfrom the store 51 six times, after which the row address generator 52 isincremented by an output pulse from the decoder 56 and the next row ofdata is read out in the same way, and so on. Thus in effect eachcomplete data waveform is generated in six successive portions, eachcorresponding to a respective state of the output of the slot counter55. Each successive portion is generated by the logic circuit 54 in suchmanner that the first portions of the data waveforms for all the (n)pixels of the selected row are generated one after the other and clockedserially into the shift register 57. When this has occurred the latch 58is enabled by an output pulse from the divider 60 , energising the rowdrivers 59 accordingly. The second portions of the data waveforms forall the pixels of the selected row are then generated one after theother by the circuit 54, clocked into the register 57 and similarly usedto energize the row drivers 59 accordingly, and so on for all portionsup to the sixth. The data waveforms for the pixels of the next selectedrow are then generated in the same way, and so on for all thesuccessively selected rows.

Referring once again to the data waveforms shown in FIGS. 4a and 5a itwill be appreciated that each data waveform to be generated by the logiccircuit 54 depends not only on the data to be represented by thatwaveform (supplied by the store 51) but potentially also on the datarepresented by the immediately preceding data waveforms supplied to therelevant column conductor 46 or on the data to be represented by theimmediately succeeding data waveform to be supplied to the relevantcolumn conductor 46 depending on the position of the further section.More particularly the first section (i.e. the first two portions) of thecurrent data waveform is potentially dependent on the data representedby the immediately preceding data waveform applied to the relevantcolumn conductor, and the last section (i.e. the last two portions) ofthe current data waveform is potentially dependent on the data to berepresented by the immediately succeeding data waveform to be suppliedto the relevant column conductor.

Thus, in order that it can generate the first two portions of thecurrent waveform correctly the logic circuit 54 needs to be suppliedwith information about the immediately preceding waveform for the samecolumn conductor; this information is present at the serial output 63 ofsecond shift register 65 at the relevant time and is supplied to theinput 62 of the logic circuit 54. Similarly, in order that it cangenerate the last two portions of the current waveform correctly thelogic circuit 54 needs to be supplied with information about theimmediately succeeding waveform for the same column conductor at therelevant time. The decoder 56 is provided to this end, incrementing therow address generator when the fourth portions of the data waveforms forthe pixels of the currently selected row have been generated (i.e. atthe end of the data section) so that the data to be represented by theimmediately succeeding waveform to be applied to the same columnconductor is applied to the input 61 of the logic circuit 54 at thetimes at which it is required to generate the fifth portion of eachcurrent data waveform.

Referring to FIG. 8, a possible construction for the logic circuit 54 ofFIG. 7 is shown, suitable for use in the normal mode to produce thewaveforms shown in FIG. 4a, with data waveform 1 represented by logic 1and data waveform 2 represented by logic 0 at input 61, and with logic 1at the first output 67 producing a positive pulse, and logic 0 at thefirst output 67 producing a negative pulse.

The logic circuit shown in FIG. 8 produces logic signals at its output67 and 68 according to the following table, it being assumed that slotcounter 55 starts counting each time with its contents equal to binary000 (slot 1) and counts in the normal binary manner to binary 101 (slot6) after which it resets to binary 000 and recommences counting. (Thebits of increasing significance of these contents are denoted by 0, 1and 2 respectively in FIG. 8).

    ______________________________________                                        Slot       Output 67      Output 68                                           ______________________________________                                        1          "0"            Input 62                                            2          "1" if both inputs                                                                           Input 62                                                       61 and 62 are "0",                                                            "0" otherwise                                                      3          Input 61       Input 61                                            4          Input 61       Input 61                                            5          "1"            Input 62                                            6          "1" if either or                                                                             Input 62                                                       both inputs 61 and 62                                                         are "0", "0" otherwise.                                            ______________________________________                                    

Logic gates 71, 72 and 73 circulate (from input 62) the datacorresponding to the previous state of the data input 61, during slots 1and 2 of each waveform, to the second output 68 which feeds the input 69of the second shift register 65, and update it to the current state ofthe data input 61 during slots 3 and 4 of each waveform. Logic gate 74ensures that the first output 67, to the first shift register 57, isalways equal to the data input 61 during slots 3 and 4 of each waveform(i.e. the data section).

Gates 75 and 77 deal with the first output 67 for slots 5 and 6, suchthat the first output 67 is always "1" during slot 5, and is also "1"during slot 6 if either or both of the inputs 62 from the second shiftregister 65 and the input 61 from the data store 51 are "0".

Finally, gates 76 and 78 deal with the case of slot 2 when both the datainput 61 is "0" and the register input 62 is "0" (i.e. waveform 2followed by 2 in FIGS. 4a and b), by then making the first output 67equal "1" for slot 2.

Although various embodiments of the invention have been described, itwill be appreciate that modifications may be made without departing fromthe scope of the invention as defined by the claims.

For example the data waveforms may be inverted in polarity, or theselect waveforms may be inverted, or all of the waveforms may beinverted.

In another example, a pair or adjacent further sections may comprise twocharge-balanced pulse pairs. Thus each further section, whether singleor one of a pair, may take the same form. This form may also comprisetwo or more portions of the same polarity; for example it may comprisetwo charge-balanced pulse pairs.

What is claimed is:
 1. A method of addressing a matrix of bistablepixels defined by areas of overlap between members of a first set ofelectrodes on one side of a layer of ferroelectric material, and membersof a second set of electrodes, which cross the members of the first set,on the other side of the layer, in which method blanking signals areapplied to the members of the first set of electrodes to effect blankingbefore unipolar select signals are applied thereto one by one to effectselective switching by simultaneously applying a chosen data waveform toeach member of the second set of electrodes, the data waveforms eachincluding a data section coinciding with a select signal, acharge-balancing section, which charge-balances the data section, andone or more further sections, wherein each single further section orpair of further sections, occurring between successive data sectionsapplied to any electrode of the second set, is itself charge-balanced,and comprises at least two non-zero portions, the further section orsections each taking a first form if the data pulses occurringimmediately before and after the said further section or sections aredifferent, such that the data pulses switch the pixel into a differentstate, and a second form if the data pulses occurring immediately beforeand after the said further section or sections are the same, such thatthe data pulses cause no switching of the pixel, the further section orsections of the first form having a duration and polarity such as to aidswitching, the further section or sections of the second form having aduration and polarity such as to inhibit switching.
 2. A method asclaimed in claim 1, wherein the further section or pair of adjacentfurther sections has no zero portion.
 3. A method as claimed in claim 1,wherein switching of a pixel from the blanked state is effected inresponse to a data section having the opposite polarity to the selectsignal, and wherein at least the portion of the further section whichportion is adjacent a data section which effects switching has the samepolarity as the data section.
 4. A method as claimed in claim 1, whereinswitching of a pixel from the blanked state is effected in response to adata section having the same polarity as the select signal, and whereinat least the portion of the further section of each data waveform whichportion is adjacent the data section of that waveform has a polaritywhich is opposite to the polarity of the data section.
 5. A method asclaimed in claim 1 wherein the data, charge-balancing and furthersections of each data waveform have equal lengths.
 6. A method asclaimed in claim 1 in which the duration of the further section orsections having the first form is different from the duration of thefurther section or sections having the second form, whereby thewaveforms are capable of being used in an addressing scheme having threetime slots.
 7. An optical modulator apparatus comprising an opticalmodulator having a matrix of bistable pixels defined by areas of overlapbetween members of a first set of electrodes on one side of a layer offerroelectric material, and members of a second set of electrodes, whichcross the members of the first set, on the other side of the layer, andan addressing waveform generator having a first set of outputs connectedto respective members of the first set of electrodes, and a second setof outputs connected to respective members of the second set ofelectrodes, the generator being arranged to generate blanking signalsfollowed by select signals at each output of the first set and,simultaneously with each select signal, a chosen data waveform at eachoutput of the second set, the data waveforms each including a datasection coinciding with a select signal, a charge-balancing section,which charge-balances the data section, and a further section, whereinthe generator is arranged to generate the data waveforms in such mannerthat each single further section, or pair of further sections occurringbetween successive data sections at each output of the second set isitself charge-balanced and comprises at least two non-zero portions, andthe generator includes means to configure the further section orsections disposed between said successively generated data sections intoa first form if successive data portions are different such that thepixel is switched by said data portions, and into a second form ifsuccessive data portions are the same such that the pixel is notswitched by said data portions, the first form having a duration andpolarity such as to aid said switching, and the second form having aduration and polarity such as to inhibit switching.